The semiconductor device industry has a market driven need to reduce the size of devices such as transistors. To reduce transistor size, the thickness of the silicon dioxide, SiO2, gate dielectric is reduced in proportion to the shrinkage of the gate length. For example, a metal-oxide-semiconductor field effect transistor (MOSFET) would use a 1.5 nm thick SiO2 gate dielectric for a gate length of less than 100 nm. Such scaling of gate dielectrics may be the most difficult issue facing the production of the next generation of MOSFETs. The increasingly small and reliable integrated circuits (ICs) will likely be used in products such as processor chips, mobile telephones, and memory devices such as dynamic random access memories (DRAMs).
Currently, the semiconductor industry relies on the ability to reduce or scale all of the dimensions of its basic devices, such as the silicon based MOSFET, to achieve the required improved operation. This device scaling includes scaling the gate dielectric, which has primarily been formed of silicon dioxide (SiO2). A thermally grown amorphous SiO2 layer provides an electrically and thermodynamically stable material, where the interface of the SiO2 layer with underlying silicon provides a high quality interface as well as superior electrical isolation properties. However, increased scaling and other requirements in microelectronic devices have created problems as the gate dielectric has become thinner, and generated the need to use other dielectric materials as gate dielectrics, in particular dielectric materials with higher dielectric constants (k).